In order to incorporate more functions and achieve better performance and lower cost, integrated circuits are formed with increasingly smaller dimensions. However, there are legacy circuits that have already been designed with greater dimensions. It is not cost effective to redesign these circuits for smaller dimensions, although the legacy circuits' design layout may be shrunk and then implemented on silicon wafers.
Since the performances of integrated circuits are often related to their sizes, some integrated circuits are preferably not shrunk. For example, analog circuits and some high-speed integrated circuits need to keep their original sizes in order to maintain their performance unchanged throughout different generations of integrated circuits. This creates a dilemma. Since these non-shrinkable integrated circuits are often integrated in the same semiconductor chips as shrinkable integrated circuits, whose performances are not affected by their dimensions, the integrated circuits on a semiconductor chip may not be able to be shrunk uniformly. Instead, efforts are needed to shrink only the shrinkable circuits, while keeping the non-shrinkable circuits intact.
To achieve this goal, the layout of the non-shrinkable circuits may be blown up (magnified) first. An abstract may then be generated from the blown-up layout of the non-shrinkable circuits. The blown-up layout and the respective abstract are then merged with the layout and the abstract of shrinkable circuit layouts to generate a new integrated circuit. Foundries can then shrink the new integrated circuit to a same scale as to which the layout of the non-shrinkable circuit was magnified. Accordingly, the layout of the non-shrinkable circuits is restored back to the original size, while the shrinkable circuits are shrunk.
The conventional methods for shrinking integrated circuits suffer from drawbacks, however. First, there is no flexibility in the handling of the shrinking. Basically, only two types of circuits can be handled in conventional methods, including the circuits that will not be shrunk and all other circuits that will be shrunk at a same ratio. If circuits in a same chip need to be shrunk with different ratios, the conventional methods cannot handle them. Second, after the non-shrinkable circuit is blown up, if it is so large that it has to overlap surrounding circuits, errors may occur, and no solution to such an error scenario has been provided.